Complementary metal-oxide-semiconductor (CMOS) devices have been the basic logic building block in the digital-dominant world for decades. Device dimensions have been continuously reduced in order to achieve higher performance as well as higher packing density. When the CMOS devices become increasingly smaller, the device drive currents become increasingly greater. The greater drive currents require that the source/drain resistances RSD be small. In conventional MOS devices, RSD is related to the doping concentration in the source/drain regions. Therefore, small RSD were achieved by increasing the dopant concentrations in source/drain extension regions and source/drain regions. In the past, the reduction in RSD could not meet the requirement of the increase in drive currents.
Schottky source/drain regions and source/drain extension regions, which included metals for forming Schottky contacts with the adjoining semiconductor materials, are thus explored for lowering RSD. The advantageous features of Schottky barrier MOS (SBMOS) devices include low fabrication cost, low thermal budget for the source and drain formation, improved carrier transport, and high scalability. However, high barrier heights between the source/drain regions and the adjoining semiconductor materials often incur high series of resistances, and hence the improvement in the drive currents is limited. Therefore, low Schottky barriers are necessary for obtaining high drive currents. In the conventional single-metal scheme in which a single metal (typically mid-gap metal) is used for forming Schottky source/drains of both p-type MOS (PMOS) and n-type MOS (NMOS) devices, the barrier heights of the Schottky junctions of NMOS devices may be reduced by increasing the dopant concentration of the semiconductor materials adjoining the junctions. However, for PMOS devices, the reduction in barrier junction heights quickly saturates the increase in boron concentration. As such, the conventional single metal scheme cannot provide adequately low Schottky barriers.
The metals used in the source/drain regions preferably have band-edge work functions, that is, for an NMOS device, the work function of the respective metal needs to be close to the conduction band of the adjoining semiconductor material. For a PMOS device, the work function of the respective metal needs to be close to the valence band of the adjoining semiconductor material. To meet this requirement, a dual-metal scheme is used for forming NMOS and PMOS devices. For example, ErSi and PtSi have been used in Schottky source/drain regions of NMOS and PMOS, respectively. FIG. 1 illustrates a conventional Schottky CMOS structure, which includes NMOS device 2 and PMOS device 4. NMOS device 2 includes Schottky source/drain extensions 6 and source/drain regions 8, while PMOS device 4 includes Schottky source/drain extensions 10 and source/drain regions 12. Schottky source/drain extensions 6 include a first metal with a low work function, such as ErSi, while Schottky source/drain extensions 10 include a second metal with a high work function, such as PtSi. Since both the first and the second metals have band-edge work functions, the barrier heights for both PMOS and NMOS devices are low.
The conventional dual-metal scheme suffers drawbacks, however. Schottky source/drain extensions 6 and 10 need to be separately formed, thus incurring a higher cost. Thus, novel CMOS structures and the methods for forming the same that may take advantage of improved performance without increasing manufacturing cost are needed.